1. Field of the Invention
This invention relates to a LSSD testable latch circuit and more particularly to a LSSD testable latch circuit that is selectively operable as a D-type edge trigger latch during systems operation and as a three stage shift register during testing and/or that has overriding set/reset asynchronous control for the D-type edge trigger latch.
2. Description of the Prior Art
As is well known to those skilled in the art, the momentary change in the input signal by which the state of a flip-flop is switched is referred to as a trigger, and the transition it causes is said to trigger the flip-flop. Asynchronous sequential flip-flop circuits, referred to in the art simply as asynchronous flip-flops, are triggered by a change of signal level. Synchronous sequential flip-flop circuits, referred to in the art as simply clocked flip-flops, are triggered by clock pulses. In a type of triggering known as level triggering, the output of the clocked flip-flop can change any time the clock is in its active level, which may be its high or low level depending upon whether positive level clocking or negative level clocking, respectively, is employed. Level triggered clocked flip-flops are sensitive to the clock pulse duration. To mitigate the well known timing problems associated with level triggering, it is considered generally better practice in the art to use clocked flip-flops which are sensitive to the transition of an input pulse rather than the pulse duration.
Examples of clocked flip-flops sensitive to pulse transition are master-slave flip-flops and edge-triggered flip-flops. A master-slave flip-flop is a combination of two cascaded clocked flip-flops called the master latch and the slave latch. The master latch is cocked during the active level of the clock and the slave latch is triggered during the transition of the clock to its inactive level. However, as is apparent to those skilled in the art, the output of the master latch can change any time the input clock is in its active level and hence the master latch is in a sense sensitive to the time duration of the input clock.
In an edge-triggered flip-flop, output transitions occur at a specific threshold level of the clock pulse; and, when the clock pulse exceeds the threshold level, the inputs are locked out and as a result the flip-flop is unresponsive to further changes in inputs until the clock pulse returns to its inactive level and another clock pulse occurs. In a D-type edge triggered flip-flop, when the D input is sampled by a clock pulse at the clock input, the resultant next state of the flip-flop is the same as the D input and independent of the present state of the flip-flop.
Certain commercially available integrated circuit (IC) flip-flop packages provide special inputs for setting or clearing a clocked flip-flop asynchronously and the inputs are referred to in the art as direct preset or direct clear. One such IC package, for example, is the SN7474 dual D-type positive-edge-triggered flip-flop, cf. "The TTL Data Book for Design Engineers", 2nd Edition, (1976), Texas Instruments Inc., page 5-22.
With the advent of large scale and/or very large scale integrated (LSI and/or VLSI) circuit technologies and the logic networks embodied therein, adequate testing of the logic network at the various manufacturing and packaging levels, e.g. component, chip, module, board, or system levels, as well as is in the field testing, requires complex testing technologies, and hence the logic networks must now be designed for testability which is compatible with the selected testing technology. One such testing technology is referred to in the art as level sensitive scan design (LSSD) testing. It has been recognized that it is desirable to have shift register latches (SRLs) which are implementable in VSLI and conform to LSSD rules, and in particular to have an SRL implementable in VLSI that conforms to LSSD rules and is operable as a D-type edge triggered latch, cf. U.S. Pat. No. 4,277,699, "Latch Circuit Operable As A D-Type Edge Trigger", D. J. Brown et al. and assigned to the common assignee herein. As is discussed in U.S. Pat. No. 4,277,699, because of their feedback configuration, D-type edge conventional triggers are very difficult to test by automatic test pattern generation without using additional input/output (I/O) terminals, and/or because such conventional triggers cannot conform to LSSD rules.
As described in the Brown et al. patent, the SRL thereof has a polarity hold latch connected to a set/reset latch. The polarity hold latch and set/reset latch are clocked by independent positive clock pulse trains, designated +C and +B, respectively, applied to an input of the polarity hold latch and set/reset latch, respectively. The clock pulses +C are derived through an inverter from complementary negative clock pulses -C, which are also fed to another input of the polarity hold latch. In addition, the polarity hold latch has another input to which another set of clock pulses designated A are fed. The three sets of clock pulses A, B and C are non-overlapping. To LSSD test the SRL, the clock C is used to set conditions, e.g. a fault effect condition, into the polarity hold latch, and then test patterns are fed to another input of the polarity hold latch designated as SCAN IN and the fault effect condition is scanned through the SRL to an observation point, i.e. terminal, in conjunction with the A and B clocks, the C clock not being used during the scanning.
As further described in the Brown et al patent, during systems operation, that is when the SRL is being used as a D-type edge trigger, the +B clock input of the set/reset latch is intraconnected to the -C clock input of the polarity hold latch. System data is fed to another input input of the polarity hold latch designated DATA and is clocked under the control of the +C clock. The A clock is not used. After a negative edge of the -C clock, the polarity hold latch follows the data input while the set/reset latch remains unchanged. On the next positive going edge of the -C clock signal, the information in the polarity hold latch is transferred to the set/reset latch.
In practice, the LSSD testing of the SRL circuit per se of the Brown et al patent is done prior to the intraconnection of the +B and -C clock inputs as aforedescribed, i.e. the intraconnection by which the SRL is made operable as a D-type edge trigger during systems operation. Since there can be literally hundreds of the SRL circuits on each chip, a corresponding number of individual pair of access inputs are needed to test each SRL individually. Furthermore, once the individual SRL circuits were tested, the aforedescribed intraconnection required to be made for each SRL in practice was a fixed one and thereby precluded LSSD testing or retesting of the individual SRL circuit per se, i.e. in the manner that it was done prior to the intraconnection, if the interconnection was not removed.
Alternatively, if a transistor switch is employed to intraconnect the inputs +B and -C of the Brown et al patent, it would require additional logic control for the transistor switches. For LSSD testing, the logic control input would be set to a given binary state which represents that the SRL is now configured for LSSD testing. The other binary state represents that the SRL is configured for system operation, and hence cannot be LSSD tested. Thus, for LSSD testing, fault effects for the aforementioned other binary state of the logic control input cannot be generated because it would provide meaningless LSSD test results. Any testing for the other binary state to the control logic input must consequently be done with other non-automatic LSSD test patterns and hence for the case of the transistor switch of the Brown et al. patent the system thereof is not fully testable through automatically generated test patterns.
Generally, the intraconnections were made subsequent to the interconnections made between the plural SRLs of the chip. The interconnections personalized the chip into one or more groups of larger circuits such as the Johnson counter described in Brown et al. Thereafter, the groups of larger circuits of the chip were tested in accordance with LSSD procedures. For the particular Johnson counter application and other similar applications, the interconnection of the SRLs of the group was amenable to using only two I/O terminals for the clock inputs of the entire group of SRLs making up the counter. However, in other applications, it is often required that a unique triggering signal, i.e. clock signal, be provided for each edge triggered SRL. It can be shown that in these other applications, the Brown et al SRL would require for each edge triggered latch three additional I/O terminals, i.e one each for the +B and -C clocks, and one for the output of the circuit which provides the triggering signal to be fed to the control inputs of the +B and -C clocks after test.
Moreover, in the case of the LSSD testing of the Brown et al individual SRLs subsequent to the intraconnection being made and/or in the case of system operation, the capability of conditioning of the individual SRL or a group of interconnected SRLs, as the case might be, to insure the individual SRL or the SRLs of the group were in a desired predetermined state, i.e. a 1 or a 0, were complex and/or not readily available and/or unreliable. This capability is particularly necessary when dealing with asynchronous events that do not occur with a definitive timing relationship with the clock signals, e.g. start up, and is particularly more acute in high speed applications.
Of the SRLs operable as edge type triggers in LSSD systems of which we are aware, such as, for example, the multiple clock signals and multiple latch combination SRL of the aforementioned U.S. Pat. No. 4,277,699 or the single clock pulse and single latch SRL of the publication entitled "Edge-Triggered Latch Design", R. A. Johnson, IBM Technical Disclosure Bulletin (TDB), Vol. 23, No. 5, October 1980, pp 2013-2014, none have asynchronous overriding set/reset control. Moreover, while the Johnson SRL arrangement requires only one clock and latch, it should be understood that there is still a need in LSSD systems for SRLs operable as edge-triggers which employ multiple latch combinations and/or multiple clocks, and that the present invention is directed to such needs.
It should also be understood that other types of clocked flip-flop arrangements in LSSD systems are known in the prior art, but these to our knowledge have been time duration sensitive, i.e. of the types employing level triggering where the output of the clocked flip-flop can change any time the clock is in its active level. Thus, for example, the latches of U.S. Pat. No. 3,783,254, "Level Sensitive Logic System", E. B. Eichelberger, and assigned to the common assignee herein, are clocked types which are sensitive to time durations of the clock pulses and hence are not sensitive to pulse transition and/or do not have overriding asynchronous set/reset control. Other examples, are the set/reset (SR) types, such as, for example, the shift register latch (SRL) described in the publication entitled "Set/Reset Shift Register Latch", D. E. Gates et al., IBM TDB, Vol. 21, No. 10, March 1979, p 4166, that is capable of being set and reset asynchronously, but which, however, requires the system clock thereof to be active to allow either the set or reset to be effective. Likewise, the clocked flip-flop described in the publication entitled "Level Sensitive Scan Design Testable Asynchronous Set/Reset Latch", F. G. Anders et al., IBM TDB, Vol. 24, No. 2, July 1981, pp 1038-1039, and those described in the aforementioned two copending patent applications are also SR types and are time duration sensitive. Clocked flip-flops of the master-slave type are described in U.S. Pat. No. 4,298,980, "LSI Circuitry Conforming To Level Sensitive Scan Design (LSSD) Rules And Method Of Testing Same", Hajdu et al., and assigned to the common assignee herein; and in the publication entitled "Power Saving Latch", E. L. Carter, IBM TDB, Vol. 22, No. 8B, January 1980, pp 3658-3660, and as such the respective master latches thereof are time duration sensitive as previously explained.
For further information regarding asynchronous flip-flops and clocked flip-flops in general and edge-triggered flip-flops in particular, reference may be made, for example, to the following, to wit: "Digital Logic And Computer Design", M. M. Mano, Prentice-Hall, Inc., 1979, Chapter 6, pp 202-255, and FIGS. 6-12 (D-type positive-edge-triggered flip-flop), p 214; and "Digital Computer Electronics: An Introduction To Microcomputers", A. P. Malvano, Second Edition, McGraw-Hill, Inc., 1983, Chapter 7, pp 90-105.
For further information regarding level sensitive scan design (LSSD) and/or LSSD testing of VLSI, reference may be made, for example, to the following, to wit: "Testing Logic Networks and Designing for Testability", T. E. Williams et al., Computer, October 1979, pp 9-21, and U.S. Pat. Nos. 3,761,695, 3,783,254, 3,784,907, 4,006,492 4,051,352, 4,051,353, 4,063,078 and 4,063,080, all assigned to the common assignee herein.